This invention relates generally to semiconductor technology, and more particularly the invention relates to Metal-Insulator-Semiconductor Transistors (MISFETs), including Metal-Oxide-Semiconductor Field-effect Transistors (MOSFETs), built in integrated circuits based on sub-micron design rules and methods of making the same.
The MISFET structure includes two spaced doped regions, called source and drain, separated by a region called the channel. Conduction of current from the source to the drain through the channel is controlled by a voltage applied to a gate electrode (e.g., metal or doped polysilicon, for example) positioned above the channel and separated therefrom by an insulator such as silicon oxide. In an enhancement mode transistor, the source and drain are of one conductivity type, such as N-type, and the channel is of opposite conductivity type, such as P-type. In the N-channel enhancement mode transistor, a positive voltage is applied to the gate electrode which causes electrons to migrate to the underlying surface of the channel region while positive carriers, or holes, are repulsed therefrom. The channel then becomes conductive and current flows from the source to the drain.
A recognized problem in MISFET devices having narrow spacing between the source and drain stems from high electrical fields, particularly near the drain, which result in hot-carrier injection from the channel and drain/source regions into the gate insulator, or hot-carrier induced generation of interface states at the gate insulator-semiconductor interface region, which degrades the device transconductance. Some of the electrons in the channel current gain sufficient energy to overcome the oxide barrier and are injected into the oxide. Trapping of electrons in the gate oxide leads to threshold voltage instability and degraded device performance.
Heretofore, the problem of "hot carrier" degradation in MISFET structures having channel lengths of 0.5-5.0 microns has been suppressed through use of a lightly doped drain (LDD) structure as disclosed, for example, by Takeda et al. "Submicrometer MOSFET Structure For Minimizing Hot-Carrier Generation", I.E.E.E. Transactions on Electron Devices, Volume Ed - 29, No. 4, April 1982, pp. 611-618. The LDD structure consists of lightly doped source/drain regions beneath the gate electrode at the edges of the gate electrode and adjacent to heavily doped source/drain regions which are laterally displaced from the gate electrode or lie slightly beneath the edges of the gate electrode. The lightly doped region, which is driven just under the gate electrode, minimizes the generation of hot carriers, and the heavily doped region provides a low resistance region which is easily contacted.
The insertion of the lightly doped region between the channel and the heavily doped region results in a graded dopant impurity profile which reduces the peak electric field. However, the dopant profile must satisfy certain boundary conditions in minimizing the peak electric field as well as moving the peak electric field beneath the edge of the gate electrode. This has become increasingly difficult to achieve as gate lengths are reduced below 0.5 micron.